1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device having a 3D structure in which a plurality of memory cells are stacked along a channel protruding vertically from a substrate, and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device maintains data stored therein even though power supply is cut off. Currently, various nonvolatile memory devices such as a flash memory and the like are widely used.
Recently, as the improvement in integration degree of a 2D nonvolatile memory device, including memory cells formed as a signal layer over a silicon substrate, approaches a theoretical limit, a 3D nonvolatile memory device having a 3D structure, in which a plurality of memory cells are stacked along a channel protruding vertically from a silicon substrate, has been proposed.
FIG. 1 is a diagram illustrating a conventional nonvolatile memory device having a 3D structure.
Referring to FIG. 1, a first gate electrode 11, separated for each block, is disposed over a substrate 10. The first gate electrode layer 11 includes a plurality of island-shaped second holes H2 arranged therein. Over the first gate electrode layer 11, a stacked structure is disposed. The stacked structure includes a plurality of interlayer dielectric layers 13 and a plurality of second gate electrode layers 14 that are alternately stacked. The stacked structure includes a pair of first holes H1 connected to each of the second holes H2. The pair of first holes H1 and the second hole H2 form a hole having a U-shape. Furthermore, a memory layer 15 is formed along the inner walls of the first holes H1 and the second holes H2, and a channel layer 16 is buried in the first holes H1 and the second holes H2. Between the first holes H1, a slit S is disposed to separate the second gate electrode 14 between the first holes H1. Reference numerals 12 and 17 represent insulating materials.
The second gate electrode 14 is used as a gate electrode of a memory cell transistor. The channel layer 16 which is buried in any one of the pair of first holes H1, one second gate electrode 14, which is contacted with the channel layer 16, and the memory layer 15 between them form a unit memory cell. Memory cells formed along the channel layer 16 buried in one of the pair of first holes H1 are referred to as first substrings. Memory cells, formed along the channel layer 16 buried in another one of the pair of first holes H1, are referred to as second substrings. The first gate electrode 11 controls connections between the first substrings and the second substrings.
In the nonvolatile memory device of FIG. 1, the following process is required to form the first and second holes H1 and H2.
First, the first gate electrode layer 11 is formed. Then the first gate electrode 11 is etched to form and opening at a location corresponding to where the second hole H2 will be formed. An insulating material is deposited in the opening to form a sacrificial layer. Then, the stacked structure of the interlayer dielectric layers 13 and the second gate electrode layers 14 is etched to form the holes H1 and to expose the sacrificial layer. The exposed sacrificial layer is removed to form the second hole H2.
According to the above-described process, a method of forming the sacrificial layer and removing the sacrificial layer is used to form the second hole H2. Therefore, the process becomes complex. That is, a process of etching the first gate electrode 11 and a process of depositing an insulating material are required to form the sacrificial layer, and another etch process is then required to remove the sacrificial layer.
Furthermore, the sidewalls of the stacked structure exposed through the first holes H1 may be attacked during the process of removing the sacrificial layer to form the second hole H2, and the first and second holes H1 and H2 may lean.
Furthermore, since the memory layer 15 is formed along the inner walls of the first and second holes H1 and H2 after the first and second holes H1 and H2 are formed, the memory layer 15 may exist even in the second hole H2 in which the memory layer 15 is not necessary.